MAROKO133 Update ai: OpenAI’s Huge New Project Is Running Into Trouble Behind the Scenes T

📌 MAROKO133 Update ai: OpenAI’s Huge New Project Is Running Into Trouble Behind th

More products, more problems.

Behind the scenes, OpenAI is working on a new AI device in collaboration with the legendary former Apple designer Jony Ive. But according to the Financial Times, it’s running into some major technical issues that could delay its release — along with some more philosophical ones, too.

The goal, per the reporting, is to make a palm-sized device without a digital display that constantly monitors its surroundings for audio and visual cues, responding to user requests where appropriate. A source described it as “like Siri, but better.”

But one of the quandaries that OpenAI and Ives are running into? Not making the AI too personable and sycophantic — which is telling, since finding that balance is a problem besetting the chatbot industry at large.

“The concept is that you should have a friend who’s a computer who isn’t your weird AI girlfriend,” the source told the FT. It should be “accessible but not intrusive.”

OpenAI acquired Ive’s startup io for $6.5 billion in May, but the details of their arrangement has largely been kept under wraps. That month, CEO Sam Altman told his staff that he planned to ship 100 million devices designed with Ives, which he described as AI “companions.” This appears to be the same device we’re hearing about now.

A key part of the design philosophy is featuring zero screens. To compensate, the small device will rely on a camera, microphone, and a speaker to interact with users. It may even use multiple cameras, according to one FT source.

Instead of being triggered by a phrase like Apple’s “Hey Siri,” the device will be “always on,” constantly gathering data so it can build its “memory,” something that other wearable AI tech has relied on, and will undoubtedly raise massive privacy concerns if it ever hits shelves.

But it sounds like OpenAI and Ive want their gadget to be more than just a wearable. It’s also being designed to sit on a desk or table, and will be roughly the size of a smartphone. Not only is it supposed to be a better Siri, as a source described, but an improvement on smart speakers like Amazon’s Alexa or Google’s Home devices.

All this is easier said than done. For one, OpenAI already struggles to rein in ChatGPT’s engaging disposition without angering its own fans. Now it needs to somehow bridge this gap in a new and lighter-weight model. “Model personality is a hard thing to balance,” a source close to the project told the FT.  “It can’t be too sycophantic, not too direct, helpful, but doesn’t keep talking in a feedback loop.”

And then there’s the hardware side of the equation.

“Compute is another huge factor for the delay,” a source close to Ive told the FT. “Amazon has the compute for an Alexa, so does Google, but OpenAI is struggling to get enough compute for ChatGPT, let alone an AI device — they need to fix that first.”

Even if those get ironed out, will there be demand to justify the billions OpenAI has invested to make this collaboration happen? ChatGPT boasts over 700 million weekly active users, the company claims, so technically it isn’t unthinkable that OpenAI could ship 100 million little AI gadgets. But as of April, it only had 20 million paying subscribers, which suggests that the vast majority of its userbase aren’t willing to shell out money for OpenAI’s products. Perhaps a physical device might be more alluring, but it’s a big gamble.

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The post OpenAI’s Huge New Project Is Running Into Trouble Behind the Scenes appeared first on Futurism.

🔗 Sumber: futurism.com

📌 MAROKO133 Update ai: Beyond Von Neumann: Toward a unified deterministic architec

A cycle-accurate alternative to speculation — unifying scalar, vector and matrix compute

For more than half a century, computing has relied on the Von Neumann or Harvard model. Nearly every modern chip — CPUs, GPUs and even many specialized accelerators — derives from this design. Over time, new architectures like Very Long Instruction Word (VLIW), dataflow processors and GPUs were introduced to address specific performance bottlenecks, but none offered a comprehensive alternative to the paradigm itself.

A new approach called Deterministic Execution challenges this status quo. Instead of dynamically guessing what instructions to run next, it schedules every operation with cycle-level precision, creating a predictable execution timeline. This enables a single processor to unify scalar, vector and matrix compute — handling both general-purpose and AI-intensive workloads without relying on separate accelerators.

The end of guesswork

In dynamic execution, processors speculate about future instructions, dispatch work out of order and roll back when predictions are wrong. This adds complexity, wastes power and can expose security vulnerabilities. Deterministic Execution eliminates speculation entirely. Each instruction has a fixed time slot and resource allocation, ensuring it is issued at exactly the right cycle.

The mechanism behind this is a time-resource matrix: A scheduling framework that orchestrates compute, memory and control resources across time. Much like a train timetable, scalar, vector and matrix operations move across a synchronized compute fabric without pipeline stalls or contention.

Why it matters for enterprise AI

Enterprise AI workloads are pushing existing architectures to their limits. GPUs deliver massive throughput but consume enormous power and struggle with memory bottlenecks. CPUs offer flexibility but lack the parallelism needed for modern inference and training. Multi-chip solutions often introduce latency, synchronization issues and software fragmentation.

In large AI workloads, datasets often cannot fit into caches, and the processor must pull them directly from DRAM or HBM. Accesses can take hundreds of cycles, leaving functional units idle and burning energy. Traditional pipelines stall on every dependency, magnifying the performance gap between theoretical and delivered throughput.

Deterministic Execution addresses these challenges in three important ways. First, it provides a unified architecture in which general-purpose processing and AI acceleration coexist on a single chip, eliminating the overhead of switching between units. Second, it delivers predictable performance through cycle-accurate execution, making it ideal for latency-sensitive applications such as large langauge model (LLM) inference, fraud detection and industrial automation. Finally, it reduces power consumption and physical footprint by simplifying control logic, which in turn translates to a smaller die area and lower energy use.

By predicting exactly when data will arrive — whether in 10 cycles or 200 — Deterministic Execution can slot dependent instructions into the right future cycle. This turns latency from a hazard into a schedulable event, keeping the execution units fully utilized and avoiding the massive thread and buffer overheads used by GPUs or custom VLIW chips. In modeled workloads, this unified design delivers sustained throughput on par with accelerator-class hardware while running general-purpose code, enabling a single processor to fulfill roles typically split between a CPU and a GPU.

For LLM deployment teams, this means inference servers can be tuned with precise performance guarantees. For data infrastructure managers, it offers a single compute target that scales from edge devices to cloud racks without major software rewrites.

Comparison of traditional Von Neumann architecture and unified deterministic execution. Image created by author.

Key architectural innovations

Deterministic Execution builds on several enabling techniques. The time-resource matrix orchestrates compute and memory resources in fixed time slots. Phantom registers allow pipelining beyond the limits of the physical register file. Vector data buffers and extended vector register sets make it possible to scale parallel processing for AI operations. Instruction replay buffers manage variable-latency events predictably, without relying on speculation.

The architecture’s dual-banked register file doubles read/write capacity without the penalty of more ports. Direct queuing from DRAM into the vector load/store buffer halves memory accesses and removes the need for multi-megabyte SRAM buffers — cutting silicon area, cost and power.

In modeled AI and DSP kernels, conventional designs issue a load, wait for it to return, then proceed — causing the entire pipeline to idle. Deterministic Execution pipelines loads and dependent computations in parallel, allowing the same loop to run without interruption, cutting both execution time and joules per operation.

Together, these innovations create a compute engine that combines the flexibility of a CPU with the sustained throughput of an accelerator, without requiring two separate chips.

Implications beyond AI

While AI workloads are an obvious beneficiary, Deterministic Execution has broad implications for other domains. Safety-critical systems — such as those in automotive, aerospace and medical devices — can benefit from deterministic timing guarantees. Real-time analytics systems in finance and operations gain the ability to operate without jitter. Edge computing platforms, where every watt of power matters, can operate more efficiently.

By eliminating guesswork and enforcing predictable timing, systems built on this approach become easier to verify, more secure and more energy-efficient.

Enterprise impact

For enterprises deploying AI at scale, architectural efficiency translates directly into competitive advantage. Predictable, latency-free execution simplifies capacity planning for LLM inference clusters, ensuring consistent response times even under peak loads. Lower power consumption and reduced silicon footprint cut operational expenses, especially in large data centers where cooling and energy costs dominate budgets. In edge environments, the ability to run diverse workloads on one chip reduces hardware SKUs, shortens deployment timelines and minimizes maintenance complexity.

A path forward for enterprise computing

The shift to Deterministic Execution is not merely about raw performance; it represents a return to architectural simplicity, where one chip can serve multiple roles without compromise. As AI permeates every sector, from manufacturing to cybersecurity, the ability to run diverse workloads predictably on a single architecture will be a strategic advantage.

Enterprises evaluating infrastructure for the next five to 10 years should watch this development closely. Deterministic Execution has the potential to reduce hardware complexity, cut power costs and simplify software deployment — while enabling consistent performance across a wide range of applications.

Thang Minh Tran is a microprocessor architect and inventor of more than 180 patents in CPU and accelerator design.

🔗 Sumber: venturebeat.com